Principal Product Engineering - HPP

Join a growing and dynamic IP team and help the development of best in class digital and mixed signal IP products. This is a tremendous opportunity to work with an experienced team focusing on development of high-performance IP related to protocols such as PCIe, USB, DPHY, and Ethernet PHYs. The role will be an important in organization responsible for IP activities in Post Silicon Bring up and Pre-Silicon integration for the Customers.

Primary Responsibilities:

1.Responsible for supporting integration/customization/post silicon deployment of CDNS Serdes IP, mainly focus on Post Silicon bring up and debug for Customers.

2.Support MPPHY and controller SOC integration reviews and integration questions.

3.Assist customers with RTL/Gate simulations and timing closure.

4.Participate and run reviews for CDNS documentations and update R&D team with the latest customer feedback.

5.Working with global (US, west and east coast) teams, which work in different time-zones.

Position Requirements:

1.M.S. Electrical or Computer Engineering (or similar degree).

2.5 years+ of overall experience.

3.Very strong experience in silicon bring up with lab equipment (Scope/Bert/PCIe exerciser/analyzer)

4.Very strong experience in PCIe protocol, PCIe LTSSM link stable analysis, PCI Compliance test.

5.Experience in Ethernet or USB or DP or JESD will be plus.

6.Experience in CTLE or DFE or VGA will be plus.

7.Verilog RTL and gate simulation experience.

8.Familiar with board design. Ability to read schematics and conduct SI/PI reviews for customer board implementation.

9.Occasional domestic and international business trips.

Preferred Qualifications:

1.Know the knowledge of Serdes.

2.Know the PCIe protocol.

其他信息
语言要求：英语